Tag: Clock Recovery Circuitry

OTN – Lesson 9 – Video 3 – OTU Layer Sink Direction Circuitry – Part 1

This post presents the 3rd of 11 Videos that covers training on Performance Monitoring at the OTU-Layer. This post focuses on the Sink-Direction OTU-Layer Atomic Functions.

OTN – Lesson 9 – Video 3 – OTU Layer Sink Direction Circuitry/Functionality – Part 1

This blog post contains a video that begins our discussion of the Sink (Receive) Direction OTU-Layer Atomic Functions.  

This Video starts with a brief re-cap of a portion of the OTSiG/OTUk_A_Sk Atomic Function (aka OTL4.4 Sink Terminal).  

In this case, I specifically call out and identify portions of this Atomic Function that we discussed in Lessons 6 or 7 and those portions that we did not.  

  • In Lesson 7, we discussed that part of the OTSiG/OTUk_A_Sk function handled OTL4.4 or OTL4.20 logical lane signals.  
  • Lesson 6 also discussed part of the OTSiG/OTUk_A_Sk function that handled the OTL3.4 lane signal.  

I also show you the differences between the OTU3 version of the OTSiG/OTUk_A_Sk function and that for OTU4.  

Late in this Video, we start to discuss that portion of the OTSiG/OTUk_A_Sk function that handles the combined (composite) OTU3/OTU4 signal.  This portion includes

  • Discussing how the OTSiG/OTUk_A_Sk function declares and clears the dLOF defect by reviewing the Frame Alignment Block – dLOF/In-Frame State Machine Diagram, and
  • Descrambling of the OTU3/OTU4 data stream.  

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