OTN – Lesson 10 – Video 7N – Extraction of a 100GBASE-R Client Signal from an ODU4 Signal

This post presents the 7th of the 7 Videos that covers training on the Peformance Monitoring of the ODUk Layer (for Non-Multiplexed Applications). This post focuses on the 100Gbps Ethernet Adaptation Sink Atomic Function, within the Sink Direction ODU-Layer Atomic Functions.

OTN – Lesson 10 – Video 7 – ODUkP/CBR_ETC100GR-g_A_Sk Atomic Function

This video discusses how the ODUkP/CBR_ETC100GR-g_A_Sk (100Gbps Ethernet Adaptation Sink) Atomic Function processes an ODU4 signal that it receives from the upstream ODUk_TT_Sk Function.  

In particular, this video discusses how this function terminates the ODU4 overhead, extracts out, processes, and terminates the OPU4 overhead before it extracts and processes the 100GBASE-R client signal.

Continue reading “OTN – Lesson 10 – Video 7N – Extraction of a 100GBASE-R Client Signal from an ODU4 Signal”

OTN – Lesson 10 – Video 1N (100Gbps Ethernet Adaptation Source) Atomic Function

This post presents the 1st of the 7 Videos that covers training on the Peformance Monitoring of the ODUk Layer (for Non-Multiplexed Applications). This post focuses on the Source Direction ODU-Layer Atomic Functions.

OTN – Lesson 10 – Video 1 – The ODUkP/CBR-ETC100GR-g_A_So (or 100Gbps Ethernet Adaptation Source) Atomic Function

Check Out the Video Below

Click HERE to Go to Video 2 – The ODUk_TT_So and OTUk/ODUk_A_So Atomic Functions

Click HERE to return to the Main Lesson 10 Page – Non-Multiplexed Applications

What We Cover in this Video

Video 1 (of the Non-Multiplexed ODU4 System Videos) covers the following topics.

  • A High-Level Review of the Non-Multiplexed ODU4 System
  • The Conversion of the ODU-Layer circuitry into their ITU-T G.798 Equivalent Atomic Functions.
  • Let’s Take a Walk through the Source Atomic Functions
    • ODUkP/CBR_ETC100GR-g_A_So Atomic Function (100Gbps Ethernet Adaptation Source Function)
      • Explanation of the meaning of the term: ODUkP/CBR_ETC100GR-g_A_So
      • What does this function do?
      • Let’s Take a Look at the ETC100GR_CP InterfaceAccepts Clock and Data from the 100GBASE-R client circuitry
      • Permits the Client Circuitry to assert the CSF bit-field within the outbound PSI Messages
    • On-Board Clock Generator
      • Synthesizes a 104,794,445.815kbps clock signal (e.g., the ODU4 bit-rate per ITU-T G.709), along with the AI_CK, AI_FS and AI_MFS output signals.
    • Lane Processing and Transcoding (Client Specific) BlockReview of PCS Lane Handling Circuitry
      • Review of PCS Encoding and the 100GBASE-R Signal
        • 64B/66B Encoding
        • Sync Header Bits
        • Alignment Marker Block
        • PCS Lanes
        • Meaning of the M0, M1, M2, M4, M5 and M6 fields within the Alignment Marker Block
      • How to Compute the BIP3 (BIP-8) byte within the Alignment Marker Block
      • Review of “PCS Lane Reordering and De-Skewing” block
      • CAUI-10 Interface
      • CAUI-4 Interface
      • 66b Block Synchronizer
      • Alignment Marker Block Synchronizer and AMB Lock
      • PCS Lane Reordering
      • Skew Measurement and Compensation
      • PCSL BIP-8 Verification
      • Fault Conditions
        • What Happens if We Cannot Achieve or Lose 66b Block Synchronization with the 100GBASE-R Data that we receive via the CAUI-4/10 Interface?
        • What Happens if We Cannot Achieve or Lose Alignment Marker block Synchronization with the 100GBASE-R Data that we receive via the CAUI-4/10 Interface?
        • What about Invalid 66b Blocks
      • On to GMP Mapping (as we Described in Lesson 4)
      • ODUkP Overhead Field Settings (as set by this Atomic Function)
      • CI_SSF -> CSF bit-field within outbound PSI Message (of OPU Frame)
      • Review of Performance Monitoring Features of the ODUkP/CBR_ETC100GR-g_A_So Function.
      • Summary of the ODUkP/CBR_ETC100GR-g_A_So Function

In Figure 1, I highlight the Atomic Function that we discuss in Video 1.

ODU4/OTU4 System with 100Gbps Ethernet Adaptation (or ODUkP/CBR_ETC100GR-g_A_So) Function Highlighted

Figure 1, Illustration of the ODU4/OTU4 System, with the Atomic Functions, that we discuss in Video 1, highlighted

You Can Also Check Out the Video Below

Click HERE to Go to Video 2 – The ODUk_TT_So and OTUk/ODUk_A_So Atomic Functions

Click HERE to return to the Main Lesson 10 Page – Non-Multiplexed Applications

What does the expression 100GBASE-R Mean?

This post defines and describes the expression 100GBASE-R for 100Gbps Ethernet Applications.


What does the expression 100GBASE-R Mean?

For Ethernet applications, the IEEE 802.3 standard states that the term 100GBASE-R represents a group (or family) of Physical Layer (e.g., 100Gbps Transceiver) devices that do the following:

  • When it transmits its data towards the PMD (Physical Medium Dependent) device, it will:
    • Encode the CGMII data into the 64B/66B PCS (Physical Coding Sublayer) code.
    • Divide (or de-multiplex) its outbound traffic into 20 PCS Lanes by routing each 66b (66 bit) block to a different PCS lane (in a round-robin manner).
    • It will often multiplex these 20 PCS Lanes into 4 or 10 physical (or electrical) lanes for CAUI-4 and CAUI-10 applications, as it transports this data out to an Optical Transceiver (or PMD), respectively.
  • When it receives data (from the PMD), it will:
    • De-multiplexes these CAUI-4/CAUI-10 physical (or electrical) lanes of traffic that it receives from the Optical Transceiver into 20 PCS Lanes.
    • Combines (or multiplexes) these 20 PCS Lanes into a single stream of traffic as it routes this data towards the MAC (Media Access Control) device.
    • Decodes this data from the 64B/66B PCS code, back into the CGMII (100Gbps Media Independent Interface) format.  

NOTE:  I do discuss some of this processing (with 100GBASE-R data) for ITU-T G.709, Annex E mandated handling (before GMP Mapping this data into the OPU4 Payload) in Lesson 10, within THE BEST DARN OTN TRAINING PRESENTATION…PERIOD!!!

In summary, these 100Gbps Ethernet devices will encode its “outgoing” data into the 64B/66B PCS code before transmitting it over some media.  

These 100Gbps Ethernet devices will also decode its “incoming” data from the 64B/66B PCS code (to restore the data to its original content) as it receives this data.

In other words, the 100Gbps Ethernet system will encode this data into the 64B/66B PCS format solely to transport this data across the communication media.  

Once this Ethernet data has arrived (at the other end of the media), the Ethernet system will decode this data (from the 64B/66B PCS format) to restore this data to its original content.

The bit-rate of this 64B/66B PCS encoded 100Gbps Ethernet data stream is 103.125Gbps ‡ 100pm.

Why Do We Encode our 100Gbps Ethernet Data into this 64B/66B PCS Code, before we transmit this data over Optical Fiber?

We encode this 100Gbps Ethernet (CGMII) data into this 64B/66B PCS Code before we:

  • Transmit this data over Optical Fiber, or
  • Map this data into an OPU4 Frame (again for transmission over Optical Fiber).

There are several reasons that we encode this data (before transmission over Optical fiber).  But the main goals are to convert this data into a format that is more conducive for transport over Optical Fiber.  More specifically, by converting this data into the 64B/66B code, we:

  • Minimize Running Disparity (e.g., maintain DC balance) with our data, and 
  • Ensure that we have no long strings of consecutive “1s” or consecutive “0s” within the data that we transport over Optical Fiber.  
  • Offer greater management capability (within our 100Gbps signal) by including Sync Bits within our 66-bit blocks.   These Sync bits permit us to designate certain 66-bit blocks as being data-blocks and other 66-bit blocks as being control blocks.  I discuss some of this in considerable detail in Lesson 10 within THE BEST DARN OTN TRAINING PRESENTATION…PERIOD!!!

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The Various 100GBASE-R Transceiver Devices

IEEE 802.3 also states that the Physical Layer (Transceiver devices) supporting the following standards, must support the 100GBASE-R PCS encoding/decoding scheme.

  • 100GBASE-CR4
  • 100GBASE-CR10
  • 100GBASE-SR4
  • 100GBASE-SR10
  • 100GBASE-KP4
  • 100GBASE-KR4
  • 100GBASE-LR4
  • 100GBASE-ER4

Please check out the post on 64B/66B encoding to learn more about that encoding scheme.

Where is this PCS Encoder/Decoder Located?

IEEE 802.3 states that the 100GBASE-R PCS block (e.g., the entity that performs the PCS Encoding/Decoding) resides between the Reconciliation Layer and the PMA (Physical Medium Attachment), as shown in Figure 1 below.

IEEE 802.3 100Gbps Ethernet Architectural Diagram

Figure 1, Architectural Positioning of 100Gigabit Ethernet (from the IEEE 802.3 Standard)

But, in a real system, this PCS Encoder/Decoder often resides in the same IC that also contains the MAC (Media Access Controller).  

Figure 2 presents an illustration of a MAC that includes the PCS Encoder and Decoder functions.

100GBASE-R Encoder and Decoder in MAC IC

Figure 2, Illustration of a Connection between the MAC and a 100Gbps Transceiver IC

This figure also shows the MAC or Switch IC exchanging data with the 100Gbs Ethernet Transceiver IC over a CAUI-4 or CAUI-10 Interface.

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