What is Running Disparity (RD)?

The Running Disparity (or RD) is defined as the difference between the number of logic 1 bits and logic 0 bits between the start of a data sequence and a particular instant in time during its transmission.


What is Running Disparity (RD)?

The Running Disparity (or RD) is defined as the difference between the number of logic 1 bits and logic 0 bits between the start of a data sequence and a particular instant in time during its transmission.

In other words, the RD for a character is the difference between the number of logic 1 bits and logic 0 bits in that character.

Hence, if there are more logic 1 bits than logic 0 bits (within a character or string of consecutive bits) then we can state that the RD is positive.

If there are more logic 0 bits than logic 1 bits then we can state that the RD is negative.

Finally, if the number of logic 1 and logic 0 bits are the same, then we can state that the RD is neutral or zero.

We can express the Running Disparity as either an integer or as a ratio:

EXPRESSING RD AS AN INTEGER NUMBER:

If you wish to express the RD of a character or string (of consecutive bits) as an integer number, then you can calculate the RD with the following equation:

RD = (Number of Logic 1 bits in the character or string) – (Number of Logic 0 bits in the character or string)

For example:  

The running disparity of the hexadecimal expression of 0x78 is 0.

To understand why this is the case, if we were to express this value in its binary format, we get 0111 1000.  The binary expression (for this value) contains four 0s and four 1s.

Thus, RD = 4 – 4 = 0

On the other hand, the running disparity of the hexadecimal expression of 0x7F is +6.

Again, if we were to express this value its binary format, we get 0111 1111.  The binary expression (for this value) contains seven 1s and one 0.

Hence, RD = 7 – 1 = +6

EXPRESSING RD AS A RATIO:

If you wish to express the RD of a character or string (of consecutive bits) as a ratio, then you would do the following:

  • Count the total number of logical “1s” in the expression.
  • Count the total number of logical “0s” in the expression.

And then express this information in the following format:

Number of Logical 1s (in character/string) :  Number of Logical 0s (in character/string)

For example:

We express the running disparity of the hexadecimal expression of 0x78 as:

4:4, which we can reduce (or simplify) to 1:1.

Likewise, we can compute and express the RD for the value 0x7F as
7:1.

Some communication and data storage system standards (such as Gigabit Ethernet/1000BASE-X, Fibre-Channel, etc.) require that the RD be maintained to as near neutral as possible.

This means that the system designer must ensure that the ratio of logical 1 bits to logical 0 bits (over time) should be kept close to 1:1.

Thus, the System Designer must follow any character/string with negative disparity with another character/string with an equal amount of positive disparity, and vice-versa.

The purpose of keeping RD to a minimum is to maintain dc balance on the transmission medium.

The System Designer must ensure that the RD does not increase without bounds.

The 8B/10B line code is a specific example of a line code that requires and exercises control over RD.

NOTE:  Controlling and monitoring RD can also be useful in detecting transmission errors.

What does the expression 100GBASE-R Mean?

This post defines and describes the expression 100GBASE-R for 100Gbps Ethernet Applications.


What does the expression 100GBASE-R Mean?

For Ethernet applications, the IEEE 802.3 standard states that the term “100GBASE-R” represents a group (or family) of Physical Layer (e.g., 100Gbps Transceiver) devices that do the following:

  • When it transmits its data towards the PMD (Physical Medium Dependent) device.  
    • It Divides (or de-multiplexes) its outbound traffic into many lanes (usually 4 or 10 physical lanes) and
    • It encodes this data into the 64B/66B PCS (Physical Coding Sublayer) code, as it performs this de-multiplexing operation
  • When it receives data (from the PMD)
    • It decodes this data from the 64B/66B PCS code, as it receives data from the PMD, over many lanes of traffic
    • Combines (or multiplexes) this multi-lane traffic into a single stream of traffic as it routes this data towards the MAC (Media Access Control) device.

In summary, these 100Gbps Ethernet devices will encode its “outgoing” data into the 64B/66B PCS code before transmitting it over some media.  These 100Gbps Ethernet devices will also decode its “incoming” data from the 64B/66B PCS code (to restore the data to its original content) as it receives this data.

Stated differently, the 100Gbps Ethernet system will encode this data into the 64B/66B PCS format solely to transport this data across the communication media.  Once this Ethernet data has arrived (at the other end of the media), the Ethernet system will decode this data (from the 64B/66B PCS format) to restore this data to its original content.

The bit-rate of this 64B/66B PCS encoded 100Gbps Ethernet data stream is 103.125Gbps ‡ 100pm.

IEEE 802.3 also states that the Physical Layer (Transceiver devices) supporting the following standards, must support the 100GBASE-R PCS encoding/decoding scheme.

  • 100GBASE-CR4
  • 100GBASE-CR10
  • 100GBASE-SR4
  • 100GBASE-SR10
  • 100GBASE-KP4
  • 100GBASE-KR4
  • 100GBASE-LR4
  • 100GBASE-ER4

Please check out the post on 64B/66B encoding to learn more about that encoding scheme.

Where is this PCS Encoder/Decoder Located?

IEEE 802.3 states that the 100GBASE-R PCS block (e.g., the entity that performs the PCS Encoding/Decoding) resides between the “Reconciliation Layer” and the “PMA” (Physical Medium Attachment), as shown in Figure 1 below.

IEEE 802.3 100Gbps Ethernet Architectural Diagram

Figure 1, Architectural Positioning of 100Gigabit Ethernet (from the IEEE 802.3 Standard)

But, in a real system, this PCS Encoder/Decoder often resides in the same IC that also contains the MAC (Media Access Controller).  Figure 2 presents an illustration of a MAC that contains the PCS Encoder and Decoder functions.

100GBASE-R Encoder and Decoder in MAC IC

Figure 2, Illustration of a Connection between the MAC and a 100Gbps Transceiver IC.  

 

Manchester Encoding

This post presents a description of the Manchester Line Code. It also describes the Manchester Line Code’s strength, weaknesses and where it is deployed.


What is the Manchester Line Code

The Manchester Line Code is a line code that transports both data and timing information on a single serial binary data stream.

The Manchester Line Code is used in the Physical Layer.

A Manchester Line Encoder works by encoding each data bit to be either low-then-high or high-then-low – for equal amounts of time.  Since this encoded data is “high” and “low” for equal times, there is no DC bias within this signal.

More specifically, IEEE 802.3 specifies that a Manchester encoder should encode a “1” bit by setting the output to a logic “low” for the first half of a bit period and then by setting the output to a logic “high” for the second half of this bit period.  This encoding scheme requires a rising clock edge at the middle of this bit period.  Conversely, IEEE 802.3 also specifies that a Manchester encoder should encode a “0” bit by setting the output to a logic “high” during the first half of a bit period and then set the output to a logic “low” for the second half of the bit period.  This situation requires that a falling clock edge occurs in the middle of this bit period.

Figure 1 presents an illustration of a data stream that is being encoded into the Manchester format.  The very top trace is that of a clock signal.  The middle signal trace contains the data (that we wish to encode).  Finally, the bottom signal trace presents the resulting encoded data.

Manchester Line Code

 

Figure 1, An Illustration of a Data Stream being encoded into the Manchester format.  

Manchester coding works by exclusive-ORing (XOR) the Original Data and the Clock signal as Table 1 presents below.

Table 1, Encoding Data into the Manchester Line Code

Manchester Encoding Algorithm

 

Where did the Manchester Line Code come from?  

The University of Manchester (in the United Kingdom) developed the Manchester Line Code.

What are its strengths?  

The Manchester Line Code has two basic strengths:

  1. It is an electrically balanced line code and has no DC bias.
  2. It provides a large number of clock edges for “clock and data recovery” at the remote receiving terminal.  The Manchester Line Code does not need to use any “Zero-Suppression” scheme.

What are its weaknesses?  

Since Manchester encoding requires a clock edge for each bit of data, the frequency content of a Manchester-encoded signal is quite high.  This fact limits the data rates that the user can transmit a Manchester encoded data stream over a band-limited channel.  In other words, the Manchester line code is not suitable for transmitting high-speed signals over band-limited channels.

Where is it used?  

10BASE-T (10Mbps Ethernet over Twisted Pair) applications use the Manchester Line Code.

Other Line Codes

  • RZ (Return to Zero)
  • NRZ (Non-Return to Zero)
  • NRZI (Non-Return to Zero-Inverted)